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Last Updated:08/24/2026 Author: Zeon
The failing record claimed "periodic short." The client was polite regarding it, that made it worse. A batch of control panel had actually been running penalty in burn-in, then began throwing random mistakes on the manufacturing flooring-- different systems, different days, no pattern any individual could discover.
We pulled one of the stopping working boards apart. Under the microscope, nothing. Under X-ray, absolutely nothing noticeable. It took an acoustic check to find it: a ceramic capacitor-- an 0805 MLCC sitting 2 millimeters from the board edge-- was cracked clean with the body, parallel to the discontinuation. The split was unseen from the exterior. It was a traditional flex crack, and it was allowing the interior electrodes touch each other intermittently.
The cause got on the style data, not the assembly line. The capacitor rested less than 1mm from the V-cut score line. When the panel was divided, the flexing stress and anxiety ran straight with the component.
A V-score is a purposeful weak line. The fabricator cuts a V-shaped groove-- typically 1/3 of the board thickness deep, from both sides-- and the board is indicated to break easily along that line when the panel is separated. It's cheap, it's quickly, and for rectangle-shaped boards it's the default panelization approach in the industry.
However right here's what the advertising and marketing glosses over: snapping a V-cut is managed fracture. When you bend the panel, tension concentrates at the V-groove tip, and the fracture propagates along the score line. That's the intended habits. The unintended part is what takes place following-- the anxiety doesn't stop at the board edge. The bending moment radiates external from the groove, across the solder joints and into anything attached to the surface within a specific range of the line.
Ifthat "anything" is a resistor, you may obtain a solder joint split-- observable, repairable, irritating. If it's a multilayer ceramic capacitor, you obtain a different video game entirely.
Ceramic capacitors are one of the most susceptible component in the entire assembly to mechanical bending, and there's a product reason: the dielectric is a terminated ceramic. Ceramic doesn't produce, it does not flex, it doesn't flaw-- it fractures. When a MLCC body is curved past its flex limitation, the crack begins at the board-side edge and runs diagonally up with the internal electrode pile, adhering to the line of maximum shear stress.
The damage is compounded by the capacitor's internal framework-- rotating layers of ceramic and steel electrodes, perhaps 100 layers in a common X7R component. A fracture doesn't need to damage the component in half to cause failing. It just requires to shift one electrode layer far enough to touch its neighbor. That's a periodic brief that comes and goes with temperature level, resonance, and board flex. The part looks fine. The datasheet claims it's great. The circuit differs.
And there's a special viciousness to MLCC fractures: they're nearly undetectable. The crack is inner, the package is molded or ended over the crack, and the classic evaluation methods-- AOI, X-ray-- regularly miss them. The crack is just dependably captured with acoustic microscopy (CSAM) or a cautious cross-section, which is why they sail through production and surface as area failures months later on.
The core question is basic: just how close is as well close? The industry answers are not consistent, which tells you something regarding how this failing mode is dealt with.
- Some board houses quote 0.5 mm as their minimal component-to-V-cut clearance
- The IPC advice and most makers require 1.0 mm from the facility of the V-groove to the closest copper or element body
- Much more conservative referrals-- including a number of EMS providers with unpleasant area backgrounds-- say 1.27 mm to 2.0 mm, and some go as high as 5mm for ceramic capacitors specifically
The spread between 0.5 mm and 5mm isn't an indication of complication. It's the distinction between "the component doesn't physically disrupt the scoring device" and "the part survives the splitting up tension." A 0.5 mm clearance pleases the very first standard. It does virtually nothing for the 2nd. The bending stress field around a V-cut does not appreciate a half-millimeter barrier-- it propagates well past it, and the reliable dammage zone depends on board thickness, product, the depth of ball game, and exactly how the separation is done.
The sensible regulation I've involved depend on, after seeing too many cracked capacitors: keep MLCCs and various other ceramic components at least 2mm from any kind of V-cut line, and treat anything closer than 1mm as an issue waiting on a production day.
Below's the part that makes this problem really harmful to a functioning connection: by the time the boards are set up and the failing appears, 3 various events can all point at each other.
The PCB producer cut the V-groove precisely to spec. The setting up home put the elements precisely where the Gerber said. The designer routed the format with the capacitor right beside the score line, since nothing in their DRC flagged it. No one broke a guideline. The rules just really did not consist of the one that mattered-- due to the fact that component-to-edge clearance isn't a standard DRC check. The majority of CAD devices do not also measure range to the panel rating line; the panelization typically occurs after the format is finished, in a separate action, commonly by a different individual.
That's the structual void. The layout engineer locations parts against a fictional board edge. The panelization engineer includes the V-cut afterward. Neither of them ever sees the consolidated picture. The crack is developed in, not made in.
The options are understood, inexpensive, and maddeningly underused:
Apply a keep-out area in the layout, not simply the panel drawing. Specify a component-free zone of a minimum of 2mm around every score line before you start directing. If your EDA tool supports design regulations, encode it-- distance from part courtyard to board edge. If it does not, it's a checklist item on every layout evaluation. The testimonial is where this obtains captured; the DRC is where it ought to be captured yet usually isn't.
Pick the splitting up approach intentionally. V-cut is the wrong tool for boards with sensitive parts near the edges. Router splitting up (tab routing with computer mouse bites or a routed profile) creates far much less flexing stress, beccause the board isn't being bent-- it's being reduced. Laser racking up or laser transmitting is another alternative, specifically for thin or breakable substratums. The price difference is genuine, however it's small compared to a field-failure examination.
If V-cut is inescapable, secure the vulnerable parts. Place dummy rails or additional outbreak tabs so the tension is soaked up prior to it gets to the element area. Orient the score line far from high-density ceramic populations. For boards where MLCCs need to sit near the side, think about flexible adhesive under the component or a series resistor-- though honestly, the design repair is generally less costly.
Test for it at the model stage, as soon as. Inhabit a panel, divided it the way manufacturing will split it, and run the making it through boards with acoustic microscopy or at minimal 500 thermal cycles. If the MLCCs split, you figure out when you have five boards, not five thousand. This set examination catches an entire class of defects-- and practically no one runs it.
The price calculus here coincides as every other avoidable problem in this market. Moving a capacitor 1.5 millimeters costs nothing at the design phase-- the routing software program doesn't bill by the millimeter. Capturing the split at prototype costs an afternoon of acoustic scanning. Finding it in manufacturing costs a halted line, a quarantine, and a failing analysis that runs for weeks. Finding it in the field sets you back the consumer partnership.
The policy is straightforward sufficient to compose on a sticky note: no ceramic component within 2mm of a V-cut line. Impose it in layout, verify it in evaluation, and validate it on the very first panel. The MLCCs will certainly thank you-- calmly, from inside their undamaged ceramic bodies, where the split never obtained a chance to start.
Article written by Zeon
Hi, I'm Zeon — 20 years in PCB and electronics manufacturing. Front-end design and R&D, components sourcing, precision SMT, DIP through-hole assembly, and complete unit assembly. That's the full path from concept to finished product, and it's the path I've walked for two decades.
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